This invention relates to a heterojunction bipolar transistor (HBT), and more specifically to a self-aligned process for fabricating emitter and base metals for a HBT that reduces base resistance.
A heterojunction bipolar transistor (HBT) is a bipolar transistor having two adjacent layers of different materials. FIG. 1 illustrates a conventional HBT 10. HBT 10 includes a collector 12, a base 14, an emitter 16, and an emitter cap 18.
Emitter metal 22 and base metals 24 are typically made in a self-aligned process. In such a process, reentry features 20 are formed in emitter 16. Reentry features 20 are ledges, overhangs, and other features with an undercut profile. Reentry features 20 are formed by selectively wet etching emitter 16. Metal is then deposited on cap 18 and base 14 to form emitter metal 22 and base metals 24, respectively. Reentry features 20 create breaks in emitter metal 22 and base metals 24 so they are not electrically shorted.
One of the goals in designing an HBT is to minimize the base resistance, which is the resistance between emitter 16 and base metal 24 through base 14. One way to minimize the base resistance is to reduce a distance D between emitter 16 and base metal 24. Distance D can be reduced by controlling the shape of reentry features 20.
As described above, reentry features 20 can be formed by selectively wet etching emitter 16 underneath a photoresist. FIGS. 2A and 2B illustrate a wet etch of an InP (indium phosphide) emitter 16 underneath a photoresist 21 in a direction perpendicular to the (100) wafer flat. This wet etch forms ledges in the InP emitter 16 that can be used as reentry features 20. FIG. 2B also shows a wet etch of an InGaAs (indium gallium arsenide) cap 18 underneath photoresist 21. This wet etch forms ramps 23 in the InGaAs cap 18 that cannot be used as reentry features.
FIGS. 2A and 2C illustrate a wet etch of the InP emitter 16 underneath photoresist 21 in a direction parallel to the (100) wafer flat. This wet etch forms ramps 26 in the InP emitter 16 that cannot be used as reentry features. However, ramps 26 can be used as means to run metal lines up to the top layer.
Unfortunately, experiments show that wet etching perpendicular to the (100) wafer flat produces ledges with insufficient overhangs. This is illustrated in FIG. 2B, where distance D1 from a base metal (not shown) to emitter 16 (created by a first reentry feature) is not sufficient to produce the overhang necessary to separate the metal deposited on base 14 and emitter cap 18.
FIG. 3A illustrates a wet etching of the InP emitter 16 underneath photoresist 21 in a direction 45 degrees from the (100) wafer flat. This wet etch forms four ledges that can be used as reentry features 20. Unfortunately, experiments show that precise alignment (e.g., to less than one degree) of the wafer is necessary or inconsistent ledge shapes will form. In some cases, even ramps and other shapes may form instead of ledges. This is illustrated in FIG. 3B, where a misalignment of the wafer causes the wet etch to form a ramp 28 underneath photoresist 21 instead of a ledge.
FIG. 4 illustrates an HBT 30 having reentry features 32 formed by a combination of dry and wet etch of emitter 16. A dry etch is first used to etch both cap 18 and emitter 16 to form vertical sidewalls down to base 14. Emitter 16 is next wet etched underneath cap 18 to create overhangs that form reentry features 32. Unfortunately, dry etch is not selective and thus requires precise control to avoid etching into base 14 and causing irreversible damage to HBT 30.
Thus, what is needed is a self-aligned process for fabricating emitter and base metal contacts while reducing base resistance in an HBT without precise alignment nor precise etch control.
In one embodiment of the invention, a method for forming a heterojunction bipolar transistor (HBT) includes forming an etch mask atop an emitter cap layer of the HBT to expose a portion of the emitter cap layer, and selectively etching the exposed portion of the emitter cap layer to (1) form a reentry feature and (2) to expose a portion of the emitter layer.
The method further includes selectively etching the exposed portion of the emitter layer to expose a portion of the base layer, and forming a metal layer over the exposed portion of the base layer and the exposed portion of the emitter cap layer.